As the integration density is continuously increasing, fin transistor structures such as Fin Field Effect Transistors (FinFETs) are attracting more attentions due to their good electrical characteristics, scalability and compatibility with the conventional manufacture processes. FIG. 1(a) is a perspective view showing a FinFET by way of example. As shown in FIG. 1(a), the FinFET comprises: a bulk Si semiconductor substrate 101; a fin formed on the bulk Si semiconductor substrate 101; a gate electrode 103 intersecting the fin 102, with a gate dielectric layer 104 disposed therebetween; and an isolation region 105 (for example, SiO2). In this FinFET, conductive channels will be created in the fin 102, specifically, in three side walls of the fin 102 (i.e., the left and right side walls and the top wall shown in the figure) under control of the gate electrode 103, as shown by arrows in FIG. 1(a). That is, portions of the fin 102 underlying the gate electrode 103 serve as a channel region, and source and drain regions are located on opposite sides of the channel region.
In the example shown in FIG. 1(a), the FinFET is formed on the bulk semiconductor substrate. However, a FinFET can also be formed on a substrate in other forms such as a Semiconductor On Insulator (SOI) substrate. Further, the FET shown in FIG. 1(a) is termed as a tri-gate FET because the three side walls of the fin 102 all can have the channels created therein. For example, a 2-gate FET can be formed by disposing an isolation layer (for example, nitride) between the top wall of the fin 102 and the gate electrode 103, in which case there is no channel created in the top wall of the fin 102.
Furthermore, in order to improve the driving capability so as to further improve the performance, it is possible to connect several fins together to form one same device. Referring to FIG. 1(b), three fins 102a, 102b and 102c are controlled by one gate electrode 103, and they may be connected to one source and one drain (not shown in the figure). As a result, the FinFET shown in FIG. 1(b) has a significantly improved driving capability. Other reference numerals shown in FIG. 1(b) are same as those corresponding ones shown in FIG. 1(a). FIG. 2 is a photo showing a profile of fins 102 and gate electrodes 103 in an actual FinFET.
However, as device feature sizes are becoming smaller continuously, it is more difficult to make gate electrodes for the fin transistors. On the other hand, conventionally contacts on the gate electrodes and contacts on source and drain regions are formed by etching contact holes and then filling conductive material(s) such as metal therein. Such a process of making the contacts becomes even more difficult in the fin transistors.
In view of the above, there is a need for a semiconductor device structure having a fin and a method for manufacturing the same.